Renesas Electronics /R7FA6M4AF /IIC0 /ICMR2

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Interpret as ICMR2

DLCS=0, SDDL=000, TMOH=0, TMOL=0, TMOS=0

Description

I2C Bus Mode Register 2

Fields

TMOS	Timeout Detection Time Select 0 (0): Select long mode 1 (1): Select short mode
TMOL	Timeout L Count Control 0 (0): Disable count while SCLn line is low 1 (1): Enable count while SCLn line is low
TMOH	Timeout H Count Control 0 (0): Disable count while SCLn line is high 1 (1): Enable count while SCLn line is high
SDDL	SDA Output Delay Counter 0 (000): No output delay 1 (001): 1 IIC-phi cycle (When ICMR2.DLCS = 0 (IIC-phi)) 1 or 2 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 2 (010): 2 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 3 or 4 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 3 (011): 3 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 5 or 6 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 4 (100): 4 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 7 or 8 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 5 (101): 5 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 9 or 10 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 6 (110): 6 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 11 or 12 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2)) 7 (111): 7 IIC-phi cycles (When ICMR2.DLCS = 0 (IIC-phi)) 13 or 14 IIC-phi cycles (When ICMR2.DLCS = 1 (IIC-phi/2))
DLCS	SDA Output Delay Clock Source Select 0 (0): Select internal reference clock (IIC-phi) as the clock source for SDA output delay counter 1 (1): Select internal reference clock divided by 2 (IIC-phi/2) as the clock source for SDA output delay counter

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